This invention relates to an integrated circuit tester including at least one quasi-autonomous test instrument.
An integrated circuit tester is used to predict how an integrated circuit device will behave in operation. A typical integrated circuit tester includes a test head having multiple tester modules, each of which has a signal terminal. Each tester module includes pin electronics circuitry which operates the module selectively in one of several operating modes, which typically include drive high, drive low, compare high and compare low. In the drive high mode, for example, the circuitry applies a logic high signal to the signal terminal, whereas in the compare low mode, the circuitry compares the voltage at the signal terminal with a low threshold value. In order to carry out a test, the test head is positioned with the signal terminals of the tester modules in contact with respective pads of a load board. The load board provides a parallel electrical interface between the signal terminals of the tester modules and the signal pins of the device under test (DUT). The load board may support connections to multiple devices in order to allow multiple devices to be tested concurrently.
The tester includes a device power supply (DPS) having force and return terminals connected through the load board to respective power supply pins of the DUT to supply operating current to the DUT. A test is executed in a succession of cycles, and for each cycle of the test, each tester module is placed in a selected one of its predetermined operating modes. In this manner, the DUT is exercised through a sequence of internal states, and the nature of the output of the DUT in each state is observed. In the case of a complex DUT, there may be many thousands of test cycles and therefore the testing can take a long time.
Two aspects of testing of an integrated circuit device are functional testing and quiescent current testing. The purpose of functional testing is to determine whether the DUT provides the expected output in each state. The purpose of quiescent current testing is to detect anomalies in current consumption by measuring the current drawn by the DUT in steady state, when there are no changes in state occurring.
FIG. 4 illustrates in simplified block form a conventional topology for an integrated circuit tester 10 for testing an integrated circuit device 14. The tester operates under control of a server 16 and includes several current measuring DPSs 18 each having force and return terminals connected to power supply pins of the DUT 14. Each DPS includes a power supply amplifier 22 which provides DC power at a voltage dependent on an analog control signal supplied by a digital-to-analog converter (DAC) 24. The output of the amplifier 22 is connected to the force terminal of the DPS through a current sensing resistor 26 and a differential amplifier 28 provides an output signal which depends on the current flowing through the sensing resistor 26. The analog output signal of the differential amplifier 28 is converted to digital form by an analog-to-digital converter (ADC) 30 which operates under control of a sampling controller 32. The digital output signal of the ADC is supplied to the server over a bus 34.
The tester has multiple tester modules 40 each including pin electronics circuitry 46 connected to a signal pin 42 of the DUT 14. The pin electronics circuitry is able to operate selectively in one of several operating modes. Each tester module 40 also includes a local vector memory 44 for storing a succession of commands, each of which may define one of the operating modes of the pin electronics circuitry 46.
The tester also includes a sequencer 48 having an instruction vector memory 50 associated therewith. In a functional test, the server increments the sequencer through a sequence of test cycles, and in each cycle the sequencer reads an instruction from the instruction vector memory and places a command on the bus 34. The tester modules read the command from the bus and use it to access the local vector memory. The data read from the vector memory is employed to place the tester module in the appropriate operating mode, e.g. drive low or compare high, for that cycle of the test.
In a quiescent current test, the instructions loaded into the vector memory 50 include an instruction to measure the current supplied by one or more DPSs in one or more target states of the device. In order to make a quiescent current measurement, the sequencer 48 sensitizes the DUT to a desired target state by stepping through the sequence of states that are necessary to reach the target state. When the DUT is in the target state, the sequencer issues a trigger to the server 16, and the server initiates the current measurement. The server programs the DPS by supplying commands relating to, for example, the current range to be measured and the number of samples to be used in measuring the current. The differential amplifier 28 and the ADC 30 measure the voltage across the sensing resistor 24 and the ADC places digital data values on the bus 34. The server reads the data values, and when sufficient data values have been read the server provides a ready signal to the sequencer to signify that the current measurement test has been completed. The sequencer then resumes operation.
When there are multiple DPSs, the server programs the several DPSs sequentially. Since the server is a multitasking computer, other server operations may take priority over programming the DPSs, with the result that the programming of the DPSs is not repeatable and it is not possible to predict from one test to another when a given DPS will make its measurement relative to another DPS.